1. Field of the Invention
The present invention generally relates to a wiring substrate and a semiconductor apparatus including the wiring substrate, for example, a wiring substrate having plural linear conductors and a semiconductor apparatus having the wiring substrate on both sides of the linear conductors.
2. Description of the Related Art
There is known a semiconductor apparatus having a semiconductor device mounted on a wiring substrate. A related art example of a semiconductor apparatus 300 having a semiconductor device 400 mounted on a wiring substrate (multilayer wiring substrate) 500 is described with reference to FIG. 1. FIG. 1 is a cross-sectional view of the related art example of the semiconductor apparatus 300 having the semiconductor device 400 mounted on the wiring substrate 500. With reference to FIG. 1, the semiconductor apparatus 300 includes the multilayer wiring substrate 500, the semiconductor device 400, solder bumps 410, and an underfill resin layer 420. A support body 510 is provided at a center part of the multilayer wiring substrate 500.
The support body 510 includes first and second surfaces 510a, 510b. A first wiring layer 610a is formed on the first surface 510a. Further, the support body 510 includes through-vias 690 penetrating through the support body from the first surface 510a to the second surface 510b. The first wiring layer 610a is electrically connected to the below-described fourth wiring layer via the through-vias 690. Further, a first insulating layer 520a is formed in a manner covering the first wiring layer 610a. A second wiring layer 620a is formed on the first insulating layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected to each other via via-holes 520x penetrating through the first insulating layer 520a. 
Further, a second insulating layer 530a is formed in a manner covering the second wiring layer 620a. A third wiring layer 630a is formed on the second insulating layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected to each other via via-holes 530x penetrating through the second insulating layer 530a. 
A solder-resist layer 550a including opening parts 550x is formed in a manner covering the third wiring layer 630a. Regions (portions) of the third wiring layer 630a that are exposed at the opening parts 550x of the solder-resist layer 550a function as electrode pads (the portions of the third wiring layer 630a that are exposed at the opening parts 550a may hereinafter also be referred to as “electrode pads 630a”). Further, the surface on which the electrode pads 630a are formed may hereinafter also be referred to as a first surface of the multilayer wiring substrate 500.
A fourth wiring layer 610b is formed on the second surface 510b of the support body 510. Further, a third insulating layer 520b is formed in a manner covering the fourth wiring layer 610b. A fifth wiring layer 620b is formed on the third insulating layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620b are electrically connected to each other via via-holes 520y penetrating through the third insulating layer 520b. 
Further, a solder-resist layer 550b including opening parts 550y is formed in a manner covering a sixth wiring layer 630b. Regions (portions) of the sixth wiring layer 630b that are exposed at the opening parts 550y of the solder-resist layer 550b function as electrode pads (the portions of the sixth wiring layer 630b that are exposed at the opening parts 550y may hereinafter also be referred to as “electrode pads 630b”). Further, the surface on which the electrode pads 630b are formed may hereinafter also be referred to as a second surface of the multilayer wiring substrate 500.
Solder bumps 680 are formed on the electrode pads 630b. The solder bumps 680 function as outer connection terminals electrically connected to corresponding terminals of a circuit board (not illustrated) such as a motherboard when mounting the semiconductor apparatus 300 on the circuit board.
The semiconductor device 400 is mounted on the first surface of the multilayer wiring substrate 500. The semiconductor device 400 may be a semiconductor integrated circuit (not illustrated) or an electrode pad (not illustrated) formed on a thin semiconductor substrate (not illustrated) made of silicon or the like. Solder bumps 410 are formed on electrode pads (not illustrated) of the semiconductor device 400.
The electrode pads (not illustrated) of the semiconductor device 400 are electrically connected to corresponding electrode pads 630a of the multilayer wiring substrate 500 via the solder bumps 410. The material of the solder bumps 410 may be, for example, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu. The underfill resin layer 420 is formed between the semiconductor device 400 and the solder resist layer 550a. 
Further, there is known a semiconductor apparatus including a wiring substrate having semiconductor devices mounted on first and second sides of the wiring substrate. Next, with reference to FIG. 2, there is described an example of a semiconductor apparatus including a wiring substrate having semiconductor devices mounted on first and second sides of the wiring substrate. FIG. 2 is a cross-sectional view illustrating a related art example of a semiconductor apparatus 700 including a wiring substrate 800 having semiconductor devices 900, 950 mounted on first and second sides of the wiring substrate 800. In FIG. 2, the semiconductor apparatus 700 includes the wiring substrate 800, the semiconductor device 900, solder bumps 910, the semiconductor device 950, and solder bumps 960.
The wiring substrate 800 includes a substrate body 810 made of silicon. The substrate body 810 has first and second surfaces 810a, 810b. A first wiring layer 820a is formed on the first surface 810a of the substrate body 810. Further, the substrate body 810 includes through-vias 830 penetrating the substrate body 810 from the first surface 810a to the second surface 810b. The first wiring layer 820a is electrically connected to the below-described second wiring layer 820b via the through-vias 830. Further, a solder-resist layer 840a is formed in a manner covering the first wiring layer 820a. Regions (portions) of the first wiring layer 820a that are exposed at opening parts 840x of the solder-resist layer 840a function as electrode pads (the portions of the first wiring layer 820a that are exposed at the opening parts 840x may hereinafter also be referred to as “electrode pads 820a”). Further, the surface on which the electrode pads 820a are formed may hereinafter also be referred to as a first surface of the wiring substrate 800.
The second wiring layer 820b is formed on the second surface 810b of the substrate body 810. Further, a solder-resist layer 840b is formed in a manner covering the second wiring layer 820b. Regions (portions) of the second wiring layer 820b that are exposed at opening parts 840y of the solder-resist layer 840b function as electrode pads (the portions of the second wiring layer 820b that are exposed at the opening parts 840y may hereinafter also be referred to as “electrode pads 820b”). Further, the surface on which the electrode pads 820b are formed may hereinafter also be referred to as a second surface of the wiring substrate 800.
Solder bumps 850 are formed on some of the electrode pads 820b. The solder bumps 850 function as outer connection terminals electrically connected to corresponding terminals of a circuit board (not illustrated) such as a motherboard when mounting the semiconductor apparatus 700 on the circuit board.
The semiconductor device 900 is mounted on the first surface of the wiring substrate 800. The semiconductor device 900 may be a semiconductor integrated circuit (not illustrated) or an electrode pad (not illustrated) formed on a thin semiconductor substrate (not illustrated) made of silicon or the like. The semiconductor device 900 may be, for example, a memory device. Solder bumps 910 are formed on electrode pads (not illustrated) of the semiconductor device 900.
The electrode pads (not illustrated) of the semiconductor device 900 are electrically connected to corresponding electrode pads 820a of the wiring substrate 800. The material of the solder bumps 910 may be, for example, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu.
The semiconductor device 950 is mounted on the second surface of the wiring substrate 800. The semiconductor device 950 may be a semiconductor integrated circuit (not illustrated) or an electrode pad (not illustrated) formed on a thin semiconductor substrate (not illustrated) made of silicon or the like. The semiconductor device 950 may be, for example, a logic device. Solder bumps 960 are formed on electrode pads (not illustrated) of the semiconductor device 950.
The electrode pads (not illustrated) of the semiconductor device 950 are electrically connected to corresponding electrode pads 820b of the wiring substrate 800. The material of the solder bumps 960 may be, for example, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu.
However, in a case of the semiconductor apparatus 300 using the multilayer wiring substrate 500, it is difficult to connect the first surface of the multilayer wiring substrate 500 and the second surface of the multilayer wiring substrate 500 without having to extend or arrange each of the wiring layers in a plan direction (i.e. X direction, Y direction, or both) due to, for example, fabrication limitations of the support body 510 or the through-vias 690. Thus, the first surface of the multilayer wiring substrate 500 cannot be connected to the second surface of the multilayer wiring substrate 500 with either a narrow pitch or at a short distance.
As in the case of the semiconductor apparatus 700, by forming the through-vias 830 with a method of forming through-holes in the silicon substrate body 810 and filling the through-holes with a metal material or the like (i.e. so-called TSV (Through Silicon Via), the first surface of the multilayer wiring substrate 500 can be connected to the second surface of the multilayer wiring substrate 500 by the through-vias 830 without having to extend or arrange the wiring layers in a plan view direction (i.e. X direction, Y direction, or both). Such a method of forming the through-vias (TSV) results in high manufacturing cost and has limitations with respect to the size of the semiconductor device to be mounted on the wiring substrate.